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rev. 1.00 1 january 05, 2017 rev. 1.00 pb february 14, 2017 ht42b532-x usb to i 2 c bridge ic usb bridge ic naming rules ht42b 5 32 -x product family ht42b = holtek bridge ic bridge series of host 5 = usb usb class type version 1 = first version bridge series of device 2 = i 2 c 3 = spi 4 = uart 3 = cdc class 6 = hid class features ? operating v oltage (v dd ): 3.3v~5.5v ? i 2 c pins v oltage (v ddio ): 1.8v~v dd (less than v dd voltage) ? fully integrated internal 12mhz oscillator with 0.25% accuracy for all usb modes which requires no external components ? usb interface ? usb 2.0 full speed compatible ? implements usb protocol composite device: C communication device class (cdc) for communications and confguration. C human interface device (hid) for user confgure usb vid, pid and device description strings ? integrated an internal 1.5k pull-high resistor on d+ pin ? serial interface C i 2 c ? supports clock rate up to 400khz ? supports master and slave modes decided by ap command ? supports maximu m 62 bytes transmit buf fer and 62 bytes receive buffer ? supports sda (master mode) and scl or sda (slave mode) pins resume signal to request a remote wake-up ? supports vddio pin for i 2 c and a0~a1 pins power supply ? support standard w indows? drivers for v irtual com port (vcp): w indows xp (sp2), v ista, windows 7, w indows 8, w indows 8.1 (only an inf fle is required) and w indows 10. ? support android 4.0 or later version and mac os x ? integrated 256 bytes internal true eeprom for user memory ? power down and wake-up functions to reduce power consumption ? package types: 8-pin sop, 10-pin msop general description the ht42b532-x is a high performance usb to i 2 c bridge c ontroller wi th fu lly i ntegrated usb a nd i 2 c interface functions, designed for applications that communicate with various types of i 2 c. the device includes a usb 2.0 full speed compatible interface which is used for pc comm ication. the device also includes a fully integrated high speed oscillator which is used for usb and i 2 c clock generator.
rev. 1.00 2 january 05, 2017 ht42b532-x selection table most features are common to all devices. the following table summarises the main features of each device. part no. description v dd usb virtual com hid fifo/buffer interface data rate i/o v dd package ht42b532-x usb to i 2 c bridge 3.3v~ 5.5v full-speed C tx: 62 bytes rx: 62 bytes up to 400khz 8sop 10msop ht42b533-x usb to spi bridge C tx: 128 bytes rx: 128 bytes up to 8mhz 10msop 16nsop ht42b534-x usb to uart bridge C tx: 128 bytes rx: 128 bytes up to 3mbps baud 8/10sop 10msop 16nsop ht42b564-x usb (hid) to uart bridge C tx: 32 bytes rx: 32 bytes up to 115.2kbps baud 10sop block diagram 3.3v regulator clock generator i 2 c vid pid configure 62b rx buffer usb phy internal oscillator external microcontroller circuitry scl d+ d- vdd gnd ht42b532-x usb to i 2 c bridge v33o vddio device power 62b tx buffer usb controller a0 sda a1 pin assignment v33o gnd a1 sda vddio scl a0 d- d+ vdd gnd vddio d- vdd v33o sda scl d+ 1 2 3 4 8 7 6 5 HT42B532-1 8 sop-a 10 9 8 7 6 1 2 3 4 5 HT42B532-1 10 msop-a package type marking 8sop ht42b532-x 10msop b532-x note: x=1 for version number.
rev. 1.00 3 january 05, 2017 ht42b532-x pin descriptions as the pin description table applies to the package type with the most pins, not all of the listed pins may be present on package types with smaller numbers of pins. pin name type description d+ i/o usb d+ line d- i/o usb d- line scl i/o i 2 c clock line sda i/o i 2 c data/address line a0~a1 o master mode address confguration pins v33o o 3.3v regulator output vddio pwr positive power supply for the scl, sda, a0, a1 pins vdd pwr positive power supply, usb bus power gnd pwr negative power supply, ground absolute maximum ratings supply v oltage ........................... v ss -0.3v to v ss +6.0v input v oltage ............................. v ss -0.3v to v dd +0.3v storage t emperature .......................... -50c to 125c operating t emperature ........................ -40c to 85c i oh t otal ............................................................ -80ma i ol t otal .............................................................. 80ma total power dissipation .................................. 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cifed unde r "absol ute ma ximum ra tings" may c ause subst antial da mage t o t his de vice. funct ional ope ration of t hese de vices a t ot her c onditions beyond those li sted in the speci fcation i s not im plied and prol onged exposure to extrem e conditi ons ma y affect device reliability. d.c. characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3.3 5.5 v v ddio vddio input voltage for i 2 c pins 1.8 v dd v i dd operating current 5v no load 11 16 ma i sus suspend current (usb) 5v suspend mode, no load, usb on, other peripherals off 360 450 a v il input low voltage for input pins 0 0.2v ddio v v ih input high voltage for input pins 0.8v ddio v ddio v i ol sink current for i/o pins 3v v ol = 0.1v ddio 4 8 ma 5v 10 20 ma i oh source current for i/o pins 3v v oh = 0.9v ddio -2 -4 ma 5v -5 -10 ma r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k i leak input leakage current 3v v in = v dd or v in = v ss 1 a 5v 1 a v v33o 3.3v regulator output v oltage 5v i v33o = 70ma 3.0 3.3 3.6 v r udp1 pull-high resistance between d+ and v33o 3.3v -5% 1.5 +5% k
rev. 1.00 4 january 05, 2017 ht42b532-x a.c. characteristics ta=25c symbol parameter test condition min. typ. max. unit v dd condition f hirc high speed internal rc o scillator 3.3v~5.5v usb mode -0.25% 12 +0.25% mhz t sst system start-up timer period i 2 c pins wake-up from power down mode scl(master mode)/scl or sda (slave mode) 16 t hirc t rstd system reset delay t ime power-on reset 25 50 100 ms power-on reset characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rr por v dd rising rate to ensure power-on reset 0.035 v/ms t por minimum time for v dd stays at v por to ensure power-on reset 1 ms v dd t por rr por v por time
rev. 1.00 5 january 05, 2017 ht42b532-x usb interface the usb interface, being usb 2.0 full-speed compatible, is a 4-wire series bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. a token based protocol method is used by the host device for communication cont rol. other advantages of the usb bus include live plugging and unplugging and dynamic de vice c onfiguration. as t he c omplexity of usb data protocol does not permit comprehensive usb operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed usb understanding. the device includes a usb interface function allowing for the convenient design of usb peripheral products. power plane there are two power planes for the device and they are the usb bus power input (v dd ) and 3.3v regulator output (v v33o ). for the usb sie vdd, it will supply power for all circuits related to usb sie and is sourced from pin vdd. onc e t he usb i s r emoved f rom t he usb and there is no power in the usb bus, the usb sie circuit is no longer operational. usb interface operation to communicate with an external usb host, the internal usb m odule ha s t he e xternal pi ns known as d+ and d- along with the 3.3v regulator output pin v33o. a serial interface engine (sie) decodes the incoming usb data stream and transfers it to the c orrect e ndpoint b uffer m emory k nown a s t he fifo. the usb module has 4 endpoints, ep0 ~ ep3. the endpoint 0 supports the control transfer while the endpoint 1 ~ endpoint 3 support the interrupt or bulk t ransfer. t he ht 42b532-x bri dge ic support s the usb c ommunication de vice c lass ( cdc) f or communications and confguration. endpoint transfer t ype 0 control 1 interrupt 2 bulk out 3 bulk in usb endpoint transfer type if there is no signal on the usb bus for over 3ms, the usb device will enter the suspend mode. the device enters the suspend state to meet the requirements of the usb suspe nd current spe cification. whe n t he resume signal is asserted by the usb host, the device will be woken up and leave the suspend mode. as t he usb de vice ha s a re mote wa ke-up fu nction, the usb device can wake up the usb host by sending a remote wake-up pulse. once the usb host receives a remote wake-up signal from the usb device, the host will send a resume signal to device. usb vid and pid confgure the device has configured the default v ender id (vid:0x04d9), pr oduct i d ( pid:0xb532) a nd product des cription s trings of u sb to i 2 c bridge. the user can update v ender id, product id, product description strings and remote wake-up setting using their application programs. this device has been configured to the default usb confguration data as shown in the following table. parameter value ( hex) usb vendor id (vid) 0x04d9 usb product id (pid) 0xb532 remote wake-up default disable manufacturer name holtek product description usb to i 2 c bridge serial number 0000 i 2 c interface the ht42b532-x contains an i 2 c function. the i 2 c interface is often us ed to communicate w ith external peripheral devices s uch as microcontrollers , s ensors, eeprom m emory e tc. or iginally d eveloped b y philips, i t i s a t wo l ine l ow spe ed se rial i nterface for synchronous seri al da ta tra nsfer. the advant age of only t wo l ines f or c ommunication, r elatively si mple communication protocol and the ability to accommodate multiple de vices on t he sa me bus ha s m ade i t a n extremely popular interface type for many applications. device slave device master device slave vdd sda scl i 2 c master/slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, s da, and s erial clock line, s cl. a s many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected t o t hese o utputs. no te t hat n o c hip se lect line exists, as eac h device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus.
rev. 1.00 6 january 05, 2017 ht42b532-x start scl sda scl sda 1 0 ack slave address stop data ack 1 1 0 1 0 1 0 1 0 0 1 0 1 0 0 i 2 c timing when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however , it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the master transmit mode and the slave receive mode. start signal from master send slave address and r/w bit from master acknowledge from slave send data byte from master acknowledge from slave stop signal from master the i 2 c se rial int erface func tion i ncludes t he following features: ? both master and slave mode ? master mode serial clock frequency up to 400khz ? 62-byte deep fifo t ransmit data buffer ? 62-byte deep fifo receive data buffer ? scl pin (master mode) wake-up function ? scl or sda pins (slave mode) wake-up function. ? i 2 c and a0~a1 pins power supply by the vddio pin i 2 c communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a da ta t ransmission a nd fnal ly a st op signal. when a st art signal is placed on the i 2 c bus, a ll d evices o n t he b us wi ll r eceive t his si gnal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the communication will be generated. during a data trans fer, note that after the 7-bit s lave addres s has been trans mitted, the follow ing bit, w hich is the 8th bit, is the read/write bit. the 8th bit will be checked by the slave device to determine whether to go into transmit or receive mode. if the 8th bit is 1 then this indicates that the mas ter device w ishes to r ead d ata f rom t he i 2 c b us, t herefore t he sl ave device must be setup to send data to the i 2 c bus as a t ransmitter. if the 8th bit is 0 t hen t his i ndicates that t he m aster wi shes t o se nd da ta t o t he i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver . before any transfer of data to or from the i 2 c bus, the application program (ap) must frstly initialise the ht42b532-x. the transmitted data is 8-bits wide and is transmitted after the slave device has acknowle dged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of d ata, t he r eceiver m ust t ransmit a n a cknowledge signal, l evel 0, be fore i t c an re ceive t he ne xt da ta byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver , then the slave transmitter will relea se the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the 62-byte fifo. when the slave receiver receives the data byte, it must generate an acknowledge bit on the 9th clock. the slave device, which is setup as a transmitter will check the 9th bit to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
rev. 1.00 7 january 05, 2017 ht42b532-x i 2 c clock t he sc l pin clock for the master m ode can be set using the holtek bridge api command to defne the desired value, as shown below. i 2 c mode scl clock value (hex) master 400khz 00 master 300khz 01 master 200khz 02 master 100khz 03 master 75khz 04 i 2 c power down and wake-up if the usb host sends a suspend signal to the ht42b532-x usb device, it will enter the suspend mode. it is recom mended to ensure t hat t he i 2 c dat a transmission or reception has been fnished before the device enters the suspend mode. the i 2 c function contains the sda pin (master mode), scl or sda pins (slave mode) wake-up functions. a falling edge on the scl/sda pin will wake up the device from the suspend mode. holtek bridge dll user guideline holtek usb bridge program holtek h as p rovided t he dl l t o b uild t he ht 42b532-x/ ht42b533-x bridge ic application programs for usb to i 2 c o r usb t o spi da ta c ommunication. t he api descriptions are described as below. ? htb_api bool opendevice(int ncom); holtek bridge operates in the format of v irtual com port. defne the com port number using the parameter. ? htb_api void closedevice(); used to turn off the bridge device. ? htb_api bool setiicdatarate(int ndr); used to configure the i 2 c data rate (for usb to i 2 c bridge). refer to holtekbridgedll.h for parameter defnition. ? htb_api bool setspidatarate(int ndr); used to configure the spi data rate (for usb to spi b ridge). r efer t o ho ltekbridgedll.h f or parameter defnition. ? htb_api bool setspimode(int nmode, int norder, int ncsb); ? refer t o holt ekbridgedll.h for pa rameter defnition. ? used t o c onfgure spi m ode 0/ 1/2/3, l sb/msb, and whether to use csb (for usb to spi bridge). ? when in the spi slave mode, csb must be enabled. ? htb_api bool setiicmode(int nmode, int naddr); ? used to confgure i 2 c master or slave mode and address. ? htb_api bool setiic_receiverend(bool back); ? used to configure when the master receiver ends transmission, i 2 c returns ack or nack. back: when the data length defined by setdirection or brread has been received, i 2 c will return ack or nack. true: ack false: nack ? after the opendevice action, this parameters default status is nack. the parameter should be confgured after opendevice and before read/write actions. ? htb_api bool setiic_restart(bool brestart); ? used t o d efine t he si gnal b ehavior whe n i n t he master mode. brestart: when the data length defined by setdirection or brread has been received or transmitted, i 2 c will generate a st op signal or restart signal. true: restart false: stop ? after t he ope ndevice a ction, t his pa rameters default status is st op. the parameter should be confgured before read/write actions. ? htb_api bool brread(char *p, dword nlen, dword&bytesread, dword dwtimeout); ? read if the i 2 c receiver returns nack, the return value is false; bytesread indicates the actual byte count being re ad, i f i t i s not e nough, c ontinue c all read function. dwtimeout indicates the waiting time for read, unit: ms.
rev. 1.00 8 january 05, 2017 ht42b532-x ? htb_api bool brwrite(char *p, dword nlen); ? write if the i 2 c receiver returns nack, the return value is false; ? htb_api bool finalize(); ? to end the current transmission. ? when in the spi master mode and csb is enabled, c alling t his f unction wi ll p ull c sb high. ? when i n t he spi sl ave m ode, c alling t his function will reset the bridge to its receiver default status. ? htb_api bool resetdevice(); ? reset bridge. this action will clear the contents already stored in the bridge fifo. ? htb_api bool slavecsbfalling(); ? when in the spi slave mode, this function is used to detect whether the master has re-enabled csb. if yes, it means the master will re-transmit commands, in which case call finalize or resetdevice to reset the bridge to its receiver default status. ? htb_api bool setdirection(byte ucdir, word uclen); ? htb_api bool pureread(char* p, word uclen,word &bytesread,dword dwtimeout); ? htb_api bool purewrite(char *p, word nlen); ? for both spi and i 2 c , before switching bewteen read and w rite, frst to set direction. ? setdirection(dir_read,len) + pureread = brread ? setdirection(dir_write,len) + purew rite = brwrite ? the setdirection function defines the total length len, pureread or purew rite supports any l ength b ut t heir t otal l ength c an no t l arger than len. ? dwtimeout i ndicates t he wa iting t ime fo r read, unit: ms. ? htb_api bool setgpiowakeup(byte); ? used to confgure gpio0/gpio1/gpio2/gpio3 with or without wake up function. ? this pa rameter i s t ransmitted i n t he form at of or. fo r e xample, t o e nable gpi o0 a nd gpi o2 wake up functions, the parameter is set as shown below: setgpiowakeup(gpio0|gpio2); ? htb_api bool setgpiopullup(byte); ? used to confgure gpio0/gpio1/gpio2/gpio3 with or without pull-high function. ? this parameter is set in the same way as the previous one. ? htb_api bool setgpioinput(byte); ? used to confgure gpio0/gpio1/gpio2/gpio3 input/output direction. ? setgpioinput(gpio1|gpio2) i ndicates gpi o1/ gpio2 are input, gpio0/gpio3 are output. ? htb_api bool setpwm(bool benable,pwm *pwm=null); ? used to confgure the desired pwm value, then the pwm signal will be generated on gpio3. ? refer to the associated bridge user manual for more details about the setup value. the pwm structure is described as below: bperiod defnes period width, unit: clock bclock defnes pwm clock frequency bactivelevel defnes active low or active high boutputmode defnes pwm signal output mode bopmode defnes pwm operating mode wduty defnes duty width, unit: clock
rev. 1.00 9 january 05, 2017 ht42b532-x example setup pwm pwm pwm; pwm.bperiod=pd_1024_clk; pwm.bclock=clk_3m; pwm.bactivelevel=active_low; pwm.boutputmode=pwm_output; pwm.bopmode=pwm_output; pwm.wduty=0x80; bool bret = setpwm(true,&pwm); read device which needs a ack response dword dw=0; char szbuf[9]={0x10,0,0,0,0,0,0,0,0}; char szread[16]; bool bret=opendevice(3); bret=setiic_receiverend(true); bret=setiicdatarate(iic_200k); bret=setiicmode(iic_master,0x51); bret=brwrite(szbuf,9); // write 8 bytes of 0 to address 0x10 bret=brwrite(szbuf,1); // write the read address 0x10 bret=brread(szread,16,dw,50); //data read back, response with ack after r ead // ends finalize(); closedevice(); write to/read from holtek eeprom ht24lc0x C using restart signal dword dw=0; char szbuf[9]={0x10,0,0,0,0,0,0,0,0}; char szread[16]; bool bret=opendevice(3); bret=setiicdatarate(iic_200k); bret=setiicmode(iic_master,0x51); bret=brwrite(szbuf,9); // write 8 bytes of 0 to address 0x10 bret=setiic_restart(true); // set before brwrite bret=brwrite(szbuf,1); // write the read address 0x10, generate restart // signal after write ends bret=setiic_restart(false); // set before brread bret=brread(szread,16,dw,50); //data read back, response with nack after r ead // ends and generate a stop signal finalize(); closedevice(); write to/read from spi flash dword dw=0; char szid[4]={0x90,0,0,0}; char szcmd[4]={0x03,0,0,0}; char szread[16]; : bool bret=opendevice(3); bret=setspidatarate(spi_4m); bret=setspimode(spi_mode0, spi_msb,spi_en_csb); bret=brwrite(szid,4); //read id bret=brread(szread,2,dw,50); finalize(); bret=brwrite(szcmd,4); bret=brread(szread,0x10,dw,50); //read 0x10 bytes from address 0x00 finalize();
rev. 1.00 10 january 05, 2017 ht42b532-x i 2 c slave mode setup description when the i 2 c is confguread to operate in the slave mode, it is to operate as a slave receiver which means to read from the usb host (bulk out). the i 2 c master terminal should follow the protocol shown in the table for normal communications. master transmitter (mt) request master transmitter (mt) command code slave receiver (sr) response wirte data available request 0xa3 buffer length read data available request 0xa4 buffer length r/ !w a master transmitting slave transmitting s r /!w r p start repeated start stop acknowledge not acknowledge write read i 2 c general address 0x00 write data available request s i 2 c general address r/ !w command code a3h r i 2 c address-7bits r /!w buffer length don t care p a a a write data s i 2 c address-7bits r/ !w 1 st data 2 nd data last byte data p a a !a read data s i 2 c address-7bits r /!w 1 st data 2 nd data last byte data p a a !a !a read data available request s i 2 c general address r/ !w command code a4h a mt : master transmitter sr : slave receiver st : slave transmitter write data : data from i 2 c interface to the host(bulk in) read data : data from host to i 2 c interface(bulk out) don t care a don t care !a r i 2 c address-7bits r /!w buffer length don t care p a a don t care a don t care !a
rev. 1.00 11 january 05, 2017 ht42b532-x write data fow (data from i 2 c interface to host: bulk in) mt write data to sr flow mt : master transmitter sr : slave receiver st : slave transmitter start write data available request buffer length=0? yes no write data end? no yes write data length buffer length write data end
rev. 1.00 12 january 05, 2017 ht42b532-x read data flow (data from host to i 2 c interface: bulk out) mt read data from sr flow mt : master transmitter sr : slave receiver st : slave transmitter start read data available request buffer length=0? yes no read data end? no yes read data length buffer length read data end product description update to implement product description update first open the holtek ht42b534-x bridge ic demo ap , if the usb had been plugged into the host pc, it will show that the usb has been openned successfully on a new window. the user can use the appli cation program to update t he c ustomer vid, pid, ma nufacturer na me, product descriptio n, serial number and 256 bytes of user m emory. it c an c onfgure t he i 2 c bri dge de vice hardware fow control and remote wake-up functions. in addition to the definable descriptions, a user memory area which is not used to store parameters is also provided for users to record data. the confguration descriptor length table is shown as below. parameter length usb vendor id(vid) 1 word (hex) usb product id(pid) 1 word (hex) manufacturer name support max. 16 characters product description support max. 32 characters serial number support max. 4 words
rev. 1.00 13 january 05, 2017 ht42b532-x application circuits 1 2 3 4 5 6 j3 iic_c on a1 sda a0 scl + c4 1uf c5 0 .1uf r1 33 v_usb 1 usb- 2 usb+ 3 vss 4 sheld 5 j1 usb_port a1 vdd sda d+ d- a0 scl c6 0 .1uf r2 33 c9 47pf c10 47pf d+ d- vdd c7 0 .1uf + c8 10uf vdd vdd 1 gnd 3 a1 4 sda 5 vddio 6 d+ 10 d- 9 a0 8 scl 7 v33o 2 u2 ht42b532_10 msop vddio 1 2 3 j2 c on3 vddio vdd v33o v33o sda scl d+ d- c2 0 .1uf vdd + c1 1uf c3 0 .1uf vddio v33o gnd 1 sda 2 vddio 3 scl 4 v330 8 vdd 7 d- 6 d+ 5 u1 ht42b532_8 sop r3 2k vddio r4 2k
rev. 1.00 14 january 05, 2017 ht42b532-x package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/ carton information . additional supplementary information with regard to packaging is liste d below . click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.00 15 january 05, 2017 ht42b532-x 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.00 bsc b 3.90 bsc c 0.31 0.51 c 4.90 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.00 16 january 05, 2017 ht42b532-x 10-pin msop outline dimensions symbol dimensions in inch min. nom. max. a 0.043 a1 0.000 0.006 a2 0.030 0.033 0.037 b 0.007 0.013 c 0.003 0.009 d 0.118 bsc e 0.193 bsc e1 0.118 bsc e 0.020 bsc l 0.016 0.024 0.031 l1 0.037 bsc y 0.004 0 8 symbol dimensions in mm min. nom. max. a 1.10 a1 0.00 0.15 a2 0.75 0.85 0.95 b 0.17 0.33 c 0.08 0.23 d 3 bsc e 4.9 bsc e1 3 bsc e 0.5 bsc l 0.40 0.60 0.80 l1 0.95 bsc y 0.1 0 8
rev. 1.00 17 january 05, 2017 ht42b532-x copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com/en/.

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